Sessions take place in the following rooms:
- SLab = Schumpeter Lecture Hall, Inffeldgasse 11, 3rd Floor
- HS i9 = Inffeldgasse 13
- HS i1 = Inffeldgasse 18
Monday, September 14, 2026
The full VSTTE program is available here: VSTTE Program.
| Time | Session |
|---|---|
| 08:30–09:00 | Coffee |
| Invited Talk: Roderick Bloem (HS i1) | |
| 09:00–10:00 | Side Channel Secure Software: A Hardware Question |
| 10:00–10:30 | Coffee Break |
| 10:30–12:00 | VSTTE |
| 12:00–13:30 | Lunch (Mensa, Inffeldgasse 10) |
| Invited Talk: Martin Jonáš (HS i1) | |
| 13:30–14:30 | Towards a Standard Intermediate Language for Software Verification |
| 14:30–15:10 | VSTTE |
| 15:10–15:40 | Coffee Break |
| 15:40–17:00 | VSTTE |
| In Memoriam: Tony Hoare (HS i1) | |
| 17:00–18:00 | TBA |
Tuesday, September 15, 2026
This day is a joint VSTTE and FMCAD Tutorial day.
| Time | Session |
|---|---|
| 08:30–09:00 | Coffee |
| VSTTE Tutorial Daniela Kaufmann (HS i1) | |
| 09:00–10:30 | A Tutorial on Algebraic Verification of Arithmetic Circuits: Gröbner Bases in Practice |
| 10:30–11:00 | Coffee Break |
| VSTTE Tutorial Omri Isac (HS i1) | |
| 11:00–12:30 | Verification of DNNs with Marabou |
| 12:30–14:00 | Lunch (Mensa, Inffeldgasse 10) |
| FMCAD Tutorial Travis Hance (HS i1) | |
| 14:00–16:00 | Verifying Rust code with Verus |
| 16:00–18:00 | Welcome Reception VSTTE & FMCAD Blauer Platz, Inffeldgasse 11 |
| 18:30 | City Tour* |
Wednesday, September 16, 2026
| Time | Track 1 – SLab | Track 2 – HS i9 |
|---|---|---|
| 08:30–09:00 | Coffee | |
| Invited Talk: Clark Barrett (SLab) | ||
| 09:00–10:00 | CSLib: Building a Platform for AI-assisted Formal Verification in Lean | |
| 10:00–10:30 | Coffee Break | |
| 10:30–12:10 | Wednesday Morning 1: SAT and MaxSAT Solving Wednesday Morning 2: Program Verification and Synthesis |
|
| 10:30–10:40 Verified Real-time Proof Checking for Large-Scale SAT Solving (short) |
10:30–10:50 Tunable Automation in Automated Program Verification |
|
| 10:40–11:00 Weight-Aware Transformations for MaxSAT |
10:50–11:10 Verifiable Checks for Business Rule Consistency |
|
| 11:00–11:10 Aperture: an Anytime, Complete and Incremental MaxSAT Solver (short) |
11:10–11:30 Synthesis with Counterexample Guided Observational Equivalence Graphs |
|
| 11:10–11:30 Understanding CDCL Solvers via Scalability Studies and Proofdoors |
11:30–11:50 An Extension API for the Concurrent Program Verifier Raven |
|
| 11:30–11:40 NobleCount: Revisiting a Forgotten Data Structure for Local Search in SAT (short) |
11:50–12:00 PSOUFFLÉ: Scaling Exact Probabilistic Logic Inference for Program Analysis (short) |
|
| 11:40–11:50 SATDiv: An Effective Solver for Diverse SAT Problem (short) |
12:00–12:10 Conditional Rewrite Rule Synthesis Using E-Graphs and Implication Propagation (short) |
|
| 12:10–13:30 | Lunch (Mensa, Inffeldgasse 10) | |
| 13:30–14:10 | Wednesday Afternoon 1: Planning and Reinforcement Learning | |
| 13:30–13:50 Multi-Agent Planning with Spatio-Temporal and Topological Constraints using STL-GO |
||
| 13:50–14:10 Requirement-Based Testing: Enhancing Reinforcement Learning with Game Theory |
||
| 14:10–15:10 | Student Forum (SLab) | |
| 15:10–16:00 | Coffee Break (with Posters) | |
| 16:00–18:00 | Wednesday Late Afternoon 1: ML-assisted Reasoning and Verification + Proofs Wednesday Late Afternoon 2: Hardware Verification |
|
| 16:00–16:20 Can LLMs Perform Synthesis? |
||
| 16:20–16:40 LLM-Powered Automatic Theorem Proving and Synthesis for Hybrid Systems and Games |
16:00–16:20 Semantics, Operations, and Properties of P3109 Floating-Point Representations in Lean |
|
| 16:40–17:00 SVAEval: An Evaluation Framework for LLM-based SVA Property Generators |
16:20–16:40 Ordering-Relation Abstraction for Formal Verification of Bubble Errors in CARRY8-Based Tapped Delay Lines |
|
| 17:00–17:20 Nazrin: An Atomic Neural Proof Automation Tactic in Lean 4 |
16:40–17:00 Certified Sequential Sweep Without Unrolling |
|
| 17:20–17:40 Trimming Pseudo-Boolean Proofs |
17:00–17:20 Lemma Pattern Matching for SMT-based Verification of Analog Mixed-Signal Hardware |
|
| 17:40–18:00 Solution Space Partitioning for Extremal Set Theory |
17:20–17:30 Formal Verification of Mixed-Signal Systems Using Real Number Modeling with SMT-based Model Checking (short) |
|
| Business Meeting | ||
| 18:00–19:00 | Details TBA | |
| 19:30–22:00 | PC Dinner | |
Thursday, September 17, 2026
| Time | Track 1 – SLab | Track 2 – HS i9 |
|---|---|---|
| 08:30–09:00 | Coffee | |
| Invited Talk: Claire Xenia Wolf (SLab) | ||
| 09:00–10:00 | The Parable of the Square-Dancing Witches and Wizards | |
| 10:00–10:30 | Coffee Break | |
| 10:30–11:50 | Thursday Morning 1: Neural Network Verification Thursday Morning 2: Decision Procedures for Arithmetic Constraints |
|
| 10:30–10:50 PICID: Proof-Driven Clause Learning in Neural Network Verification |
10:30–10:50 MCSAT Modulo Transcendental Arithmetics |
|
| 10:50–11:10 Incremental Neural Network Verification via Learned Conflicts |
10:50–11:10 Extending an SMT Solver with LIA⋆ Constraints |
|
| 11:10–11:20 Talking with Verifiers: Automatic Specification Generation for Neural Network Verification (short) |
11:10–11:30 Randomized Satisfiability Checking for Non-Linear Arithmetic over Finite Fields |
|
| 11:20–11:40 Optimized Piecewise Affine Abstractions of Neural Networks with Learnable Activation Functions |
11:30–11:50 F-QLPs over unit relative constraints |
|
| 11:50–13:10 | Lunch (Mensa, Inffeldgasse 10) | |
| 13:10–14:10 | Thursday Early Afternoon 1: Runtime Monitoring and Specification Learning Thursday Early Afternoon 2: Specifications and Automata |
|
| 13:10–13:30 Multi-Property Temporal Logic Monitoring |
13:10–13:30 On the Hierarchy of Finite-Word Hyperlanguages |
|
| 13:30–13:50 Shrinking Mission-time LTL Runtime Monitors with Equality Saturation |
13:30–13:50 Symbolic Automata for MTL0,inf with Super-Dense Semantics |
|
| 13:50–14:00 Learning GR(1) Specifications from Traces (short) |
13:50–14:00 Translating LTL to Lasso Automata (short) |
|
| 14:10–22:00 | Social Event Bus trip to the countryside! We take off from Blauer Platz, Inffeldgasse 13 | |
Friday, September 18, 2026
| Time | Track 1 – SLab | Track 2 – HS i9 |
|---|---|---|
| 08:30–09:00 | Coffee | |
| Invited Talk: Laura Kovács (SLab) | ||
| 09:00–10:00 | The Vampire Diary | |
| 10:00–10:30 | Coffee Break | |
| 10:30–12:10 | Friday Morning 1: Proofs and Proof Generation Friday Morning 2: Model Checking and Symbolic Representation |
|
| 10:30–10:50 DSLean: A Framework for Type-Correct Interoperability Between Lean 4 and External DSLs |
10:30–10:50 On the Complexity of Word-Level Model Checking with Arrays |
|
| 10:50–11:10 Proof Production for Satisfiability Modulo Finite Fields with Proof Checking in Pacheck and Lean |
10:50–11:10 CB-VER: A Stable Foundation for Modular Network Control Plane Verification |
|
| 11:10–11:30 Certifying optimal MEV strategies with Lean |
11:10–11:30 Certificate-Aware Property-Directed Reachability |
|
| 11:30–11:50 IsaAbduct: A Multi-Strategy Abduction Pipeline for Isabelle/HOL |
11:30–11:50 Validated Binary Decompilation Without Tears |
|
| 11:50–12:00 Lean Certified Bitvector Solving without Bitblasting (short) |
11:50–12:10 Binary Decision Diagrams Unchained |
|
| 12:00–12:10 Optimising Constant Matrix Multiplication Circuits is NP-complete (short) |
||
| 12:10–13:30 | Lunch (Mensa, Inffeldgasse 10) | |
| 13:30–15:10 | Friday Early Afternoon 1: Verification for Security and Privacy Fr Early Aftermoon 2: Software Verification |
|
| 13:30–13:50 SymCert: Verifying SMT-Based Policy Analyses |
13:30–13:50 Verifying a Memory Allocator for Rust |
|
| 13:50–14:10 PolyGram: A Certifying Compiler for Network Policies |
13:50–14:10 Formal Verification of a Memory Allocator for Rust Hypervisors: From Verified to Deployable Code with Functional Equivalence Guarantees |
|
| 14:10–14:30 Efficient Enumeration of Cloud Access Permissions |
14:10–14:30 Prophecy Variables and Invariants in the Move Prover |
|
| 14:30–14:50 Privacy-Preserving Robust Monitoring of Dense-Time Temporal Logic |
14:30–14:50 Formal Verification of Imperative First-Class Functions in Move |
|
| 14:50–15:10 Checking Information Flow in Cloud-based IoT Access Control Policies |
14:50–15:10 Multi-Threaded Software Model Checking via Parallel Trace Abstraction Refinement |
|
| 15:10–15:40 | Coffee Break | |
| 15:40–17:30 | Friday Late Afternoon 1: Probabilistic Verification and Games Friday Late Afternoon 2: Parallel and Efficient Solving Strategies |
|
| 15:40–16:00 dtControl2+ε: Trading Optimality for Explainability in MDPs via Decision Trees |
15:40–16:00 Parallel SMT Solving via Dynamic Partitioning, Core-Guided Pruning, and Backbone Detection |
|
| 16:00–16:20 Property-driven Causal Abstractions for Markov Decision Processes |
16:00–16:10 ParaProofa: A Certifying Parallel Cube-and-Conquer QBF-Solving Framework (short) |
|
| 16:20–16:40 Conditional Sampling of Symbolic Markov Chains |
16:10–16:20 Parallel SAT Sweeping on CNFs (short) |
|
| 16:40–17:00 Stochastic Boolean Satisfiability for Two-Player Sequential Games under Uncertainty |
16:20–16:40 Parallelizing Congruence Closure |
|
| 17:00–17:10 The Game Graph Gym (short) |
16:40–17:00 Beyond Lemma Sharing — Novel Parallelization Strategies for PDR |
|
| 18:00–??:?? | Board Games* | |
* Optional and free of charge.